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Tanner S-Edit is an easy-to-use design environment for schematic capture and design entry. It gives you the power you need to handle your most complex mixed-signal IC design capture. S-Edit is tightly integrated with Tanner T-Spice, Analog FastSPICE (AFS), or Eldo simulators, the Tanner L-Edit IC layout tool, and the Calibre LVS and PEX tools. S-Edit helps you meet the demands of today’s fast-paced market by optimizing your productivity and speeding your concepts to silicon. A faster design cycle gives you more flexibility in moving to an optimal solution, freeing up more time and resources for process corner validation. The results are less risk downstream, higher yield, and quicker time to market.

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Features and Benefits:

  •  Handles your most complex, fullcustom IC schematic capture
  • Integration with T-Spice, AFS, and Eldo simulators, allowing waveform cross-probing and direct viewing of operating point simulation results in the schematic
  • Export formats: SPICE, EDIF, Verilog, and VHDL
  • Import formats: Native OpenAccess, EDIF, SPICE, and Verilog
  • Support for inherited connections
  • Cross-probe between schematic, layout, and Calibre LVS report with net/device highlighting
  • Configurable schematic Electrical Rule Checks (ERC)
  • Multiple-views per cell including: SPICE, schematic, Verilog, Verilog-A, and Verilog-AMS views
  • Advanced array and bus support
  • Integrated with Tanner L-Edit Schematic Driven Layout (SDL) module to speed the layout and ECO process
  • Multiple library support with integrated library browser
  • Integration with third-party revision control tools
  • Fully scriptable and expandable using TCL/Tk command language
  • Offers easy interoperability with third-party tools and foundry PDKs
  • Platform independence on Windows or Linux
  • Ease of use: intuitive and quick learning curve
  • Unparalleled customer support
  • Flexible licensing