The Calibre PERC reliability platform is specifically designed to perform a wide range of complex reliability verification tasks using both standard rules from the foundry and custom rules created by a design team. Users can insert reliability verification into their existing design flows with Calibre PERC as part of an integrated Calibre platform for cell, block, and full-chip verification. Combining rules expressed in SVRF and the Tcl-based TVF language across all applications provides users with flexibility to meet the specific and evolving needs of their design teams, while ensuring compatibility with all foundries.
