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The Calibre PERC reliability platform is specifically designed to perform a wide range of complex reliability verification tasks using both standard rules from the foundry and custom rules created by a design team. Users can insert reliability verification into their existing design flows with Calibre PERC as part of an integrated Calibre platform for cell, block, and full-chip verification. Combining rules expressed in SVRF and the Tcl-based TVF language across all applications provides users with flexibility to meet the specific and evolving needs of their design teams, while ensuring compatibility with all foundries.

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Features and Benefits:

  • Improve design reliability –Eliminate potential electrical violations that can reduce product life or cause catastrophic electrical failure
  • Improve design accuracy – Same trusted device recognition as Calibre nmLVS; part of award-winning Calibre product line
  • Zero risk
    • Fully compatible with the Calibre platform, Calibre PERC integrates easily into existing signoff flows
  • Reduce time to market – Timely execution ensures production schedules are maintained
  • Advanced reliability verification
    • Processes the most complex circuit reliability requirements of today’s leading-edge technologies
  • Automated checking – Insert reliability checks into existing design flows for cell, block, and full-chip verification