Features and Benefits:
- Support for C/C++ and SystemC: Catapult supports both C/C++ and SystemC, giving designers the freedom to use the language that they are most comfortable with.
- High productivity: Catapult can generate verification components that are up to 80% less code than Verilog or VHDL. This can save designers a significant amount of time and effort.
- High performance: Catapult can generate verification components that achieve high performance. This is due to the fact that Catapult uses a number of sophisticated optimization techniques.
- Verification: Catapult includes a number of verification features that can help designers to verify their designs, such as coverage analysis, assertion checking, and fault simulation.
- Integration: Catapult can be integrated with a variety of other tools, such as simulators, emulators, and formal verification tools.
- Faster time to market: Catapult can help designers to achieve faster time to market by reducing the amount of time that is spent coding and verifying verification components.
- Improved quality: Catapult can help designers to improve the quality of their designs by helping them to identify and fix design flaws early in the design process.
- Lower cost of verification: Catapult can help designers to reduce the cost of verification by helping them to reduce the number of iterations in the verification process.
- Increased confidence: Catapult can help designers to increase their confidence in their designs by providing them with a comprehensive set of verification features.
- Catapult supports a variety of technologies, including CMOS, BiCMOS, and RF.
- Catapult can be used to verify a variety of designs, including chips, modules, and systems.
- Catapult is available as a stand-alone tool or as an integrated part of the Siemens EDA suite.